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Author: Admin | 2025-04-28
Introduction of heterogeneous blocks are very important in decreasing FPGA areaMeasuring the Gap between FPGAs and ASICs Speed • Hard DSP blocks increase delay? • The multipliers are fixed size, thus will slightly decrease performance, but the additional time comes with extra routing to accommodate for fixed positions of DSPs. • Memories • 3.2 -> 2.3, offer speed-up vs. ASIC design, but slow low power memory is used in the ASIC, and is no real advantage vs. newer memory • Overall, the memory blocks offer the same advantage as the DSP blocks: primary benefit is improved area efficiencyMeasuring the Gap between FPGAs and ASICs Speed • Fastest speed is useful for understanding the best case solution, but not fair to ASIC. • ASICs are generally designed for worst-case process • As seen the performance gaps are respectively larger, confirming that ASICs perform faster then FPGAs. • 2.8 times fasterMeasuring the Gap between FPGAs and ASICs Power Consumption • FPGAs consume 9-to-12 times the amount of power as an ASIC • Area savings suggest a slight power reduction as less wires & components are used • Introducing DSP and/or memory blocks to the FPGA reduce power consumptionMeasuring the Gap between FPGAs and ASICs • Presented empirical measurements quantifying the gap between FPGAs and ASICs • FPGA design is 21-40 times larger than an standard-cell ASIC design • FPGA is 2.1-4.5 times slower than a standard-cell ASIC design • FPGA consumes 9-12 times more power than ASICSegue Clearly ASICs have better performance than FPGAs, though they lack the flexibility So why are FPGAs even used?(When) Will FPGAs Kill ASICs? Non-performance factors: • Unit costs • Non Recurring Engineering (NRE) costs • Time to market • System reconfigurability • Design cycle • Volume/Gate Count/Freq/IP requirements(When) Will FPGAs Kill ASICs? • Unit cost analysis • ASIC: lower unit costs for high volumes • ASIC: design tools tend to cost more • FPGA: No upfront NRE - costs typically associated with an ASIC design(When) Will FPGAs Kill ASICs? • Exploding (NRE) ASIC Cost High mask costs as process geometry decreases(When) Will FPGAs Kill ASICs? • Time to market(When) Will FPGAs Kill ASICs? • System reconfigurability Lack of reconfigurability is a large opportunity cost of ASICs as FPGAs offer flexible design cycle management(When) Will FPGAs Kill ASICs? • Design Cycle ASIC: very unforgiving (no late changes) FPGA: flexible to allow late design changes(When) Will FPGAs Kill ASICs? • Volume Requirements (Unit cost) ASICs are cost effective for large volumes (> 250,000)(When) Will FPGAs Kill ASICs? • Gate Count Requirements FPGAs have limited gate count: 3 million (2000)(When) Will FPGAs Kill ASICs? • Performance Requirements (Speed) FPGAs can operate up to 200Mhz (2000) Note: 550Mhz Xilinx Virtex-5
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